Introduction to Programming
Makefiles
Makefiles make the process of compiling your project a little easier.
They come in really handy later, as projects get more complicated and
possibly include more than one file. Here's a very simple example of a makefile:
avoid: avoid.c
gcc avoid.c -o avoid -lcurses
Note that the second line has an actual TAB, and not just a bunch of spaces.
This is important to get right, or the Makefile will not work. Yes, Makefiles really
are that picky.
This is a way to make compiling my "avoid" example easy. Just put the text above
into a file called "Makefile" (Note the capital M!) in the same directory as avoid.c,
and type "make" at the command line. The Makefile takes care of the rest for you.
Here's how to write your own makefile. Remember, blue text is stuff you replace
with your own filenames, etc.
target: dependencies
command line
In other words, the simplest Makefile consists of:
- Target This is the name of the executable you will be making.
- Colon Two little dots, one on top of the other ":"
- Dependencies These are the files your executable depends on.
Usually these are just the .c file (or .c files) you wrote for it.
- Newline The rest goes on the second line of the file...
- Tab That magical key above the caps-lock which indents a whole bunch with only a single key-press!
- Command Line This is whatever you type into the command line in order to compile your code. Hint: It usually starts with "gcc".